Senior Test Engineer


  • Located in Sunnyvale, CA
  • Test Engineering department
  • Primary Job Responsibilities:
  • Test program development for ATE.
  • Design of hardware (ATE load boards, probe cards and sockets) that are capable of handling high data rate differential signaling.
  • Test pattern translation for functional and structural patterns.
  • Ownership of test pattern debug on first silicon.
  • Create characterization test programs and generate characterization reports.
  • Work with Design, DFT, and Product Engineering teams to define/implement SOC ATE test solutions.
  • Drive new products from conception through volume production release.
  • Yield optimization and test time reduction.
  • Implement continuous improvement to maximize test program quality.
  • Production support of test hardware (sockets, probe cards and load boards) and low yield analysis for abnormal lots.

Education/Experience Requirement:

  • BSEE required, MSEE preferred.
  • 6+ years of experience with high speed mixed-signal testers.
  • Knowledge of DFT and strong programming background (Perl, Visual Basic, C++).
  • Excellent planning and problem solving skills with the ability to multitask in a fast paced and limited resource environment.
  • Analytical, motivated and result oriented creative thinker.
  • Excellent communication and interpersonal skills.
  • Team player, independent and a self starter.
  • Ability to establish clear goals and formulate execution plans.

601, 6th Floor, B-1, Cerebrum IT Park
Kalyani Nagar, Pune -411 006